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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-19 12:32:40 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-19 12:32:40 -0800 |
| commit | 2a8e5bf9535a25bba9c9c11fc7e40d5a08958d4c (patch) | |
| tree | 11fe86a3d1c5cd988593782125fc06cd26a98294 /backends | |
| parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
| parent | 11480b4fa3ba031541e22b52d9ccd658a3e52ff1 (diff) | |
| download | yosys-2a8e5bf9535a25bba9c9c11fc7e40d5a08958d4c.tar.gz yosys-2a8e5bf9535a25bba9c9c11fc7e40d5a08958d4c.tar.bz2 yosys-2a8e5bf9535a25bba9c9c11fc7e40d5a08958d4c.zip | |
Merge pull request #805 from eddiehung/dff_init
write_verilog to write initial statement for initial flop state
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 60668f1f0..d351a6266 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1310,6 +1310,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + std::stringstream ss; + dump_reg_init(ss, cell->getPort("\\Q")); + if (!ss.str().empty()) { + f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); + f << ss.str(); + f << ";\n"; + } + } } void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) |