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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 15:05:49 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 15:05:49 -0800 |
| commit | 0e4285ca0d92397490768e649626cfdb5a0c9d95 (patch) | |
| tree | 32483f54179fa66e2904b161a03fb7925730e82d /backends | |
| parent | 588a713b5443ee4cec8479808a19785c9eadcc23 (diff) | |
| download | yosys-0e4285ca0d92397490768e649626cfdb5a0c9d95.tar.gz yosys-0e4285ca0d92397490768e649626cfdb5a0c9d95.tar.bz2 yosys-0e4285ca0d92397490768e649626cfdb5a0c9d95.zip | |
abc9_ops: generate flop box ids, add abc9_required to FD* cells
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 20f2385f6..268be432a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -596,7 +596,11 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - auto r = cell_cache.insert(cell->type); + IdString derived_type = box_module->derive(box_module->design, cell->parameters); + box_module = box_module->design->module(derived_type); + log_assert(box_module); + + auto r = cell_cache.insert(derived_type); auto &v = r.first->second; if (r.second) { int box_inputs = 0, box_outputs = 0; |