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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:47:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:47:20 -0700 |
| commit | 0e3e647596db296e662348625c28b76215b55bcf (patch) | |
| tree | 6661b71b15550b233f258eac783c1fc31bb04de6 /backends | |
| parent | f54edf1e78fbcbd8a11c2ffcbdf62a50b93ce909 (diff) | |
| download | yosys-0e3e647596db296e662348625c28b76215b55bcf.tar.gz yosys-0e3e647596db296e662348625c28b76215b55bcf.tar.bz2 yosys-0e3e647596db296e662348625c28b76215b55bcf.zip | |
Handle COs driven by 1'bx
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 12b23cfe9..42f54209b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -355,10 +355,16 @@ struct XAigerWriter } int offset = 0; - for (const auto &b : rhs.bits()) { + for (auto b : rhs.bits()) { SigBit I = sigmap(b); - if (I != b) - alias_map[b] = I; + if (b == RTLIL::Sx) + b = RTLIL::S0; + else if (I != b) { + if (I == RTLIL::Sx) + alias_map[b] = RTLIL::S0; + else + alias_map[b] = I; + } co_bits.emplace_back(b, cell, port_name, offset++, 0); unused_bits.erase(b); } |