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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 13:52:43 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 13:52:43 -0700 |
| commit | f8e470c1d1178680034a28a9f28b161acf667701 (patch) | |
| tree | 56df7f3af384b991d1271f7d53b80ee5dd0f0fd4 /backends/verilog/verilog_backend.cc | |
| parent | 5939b5d636f80d4f9345f5b8d0247332d533b68c (diff) | |
| parent | 7a58ee78dc8bd2c257498dc947081a1bba7bb54f (diff) | |
| download | yosys-f8e470c1d1178680034a28a9f28b161acf667701.tar.gz yosys-f8e470c1d1178680034a28a9f28b161acf667701.tar.bz2 yosys-f8e470c1d1178680034a28a9f28b161acf667701.zip | |
Merge pull request #1202 from YosysHQ/cmp2lut_lut6
cmp2lut transformation to support >32 bit LUT masks
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions