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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-30 15:12:39 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-30 15:12:39 +0200 |
| commit | eb571cba6a8a2a53b179578d07798517addac7c0 (patch) | |
| tree | bd7a407e5d965bec29032b0ba2bfad66f5b2eb6d /backends/verilog/verilog_backend.cc | |
| parent | 3a7d5d188d4b9cfeb225e0f5dea07ee7a40eceed (diff) | |
| download | yosys-eb571cba6a8a2a53b179578d07798517addac7c0.tar.gz yosys-eb571cba6a8a2a53b179578d07798517addac7c0.tar.bz2 yosys-eb571cba6a8a2a53b179578d07798517addac7c0.zip | |
Replaced $__alu CO/CS outputs with full-width CO output
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions