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author | whitequark <whitequark@whitequark.org> | 2019-07-08 12:29:08 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2019-07-08 12:29:08 +0000 |
commit | b1f400aeb8de657d5fa28c153df14246378df2b1 (patch) | |
tree | 92f5945f639a656983c6a926d339b6cfed0a2e5e /backends/verilog/verilog_backend.cc | |
parent | 93bc5affd3fc635dafec3a37bf4c5b94c252036f (diff) | |
download | yosys-b1f400aeb8de657d5fa28c153df14246378df2b1.tar.gz yosys-b1f400aeb8de657d5fa28c153df14246378df2b1.tar.bz2 yosys-b1f400aeb8de657d5fa28c153df14246378df2b1.zip |
genrtlil: emit \src attribute on CaseRule.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions