generate only simple assignments in verilog backend

1 files changed, 9 insertions, 5 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9523f4a52..f8b5b0e3e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1546,11 +1546,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	f << stringf("%s" "assign ", indent.c_str());
-	dump_sigspec(f, left);
-	f << stringf(" = ");
-	dump_sigspec(f, right);
-	f << stringf(";\n");
+	int offset = 0;
+	for (auto &chunk : left.chunks()) {
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, chunk);
+		f << stringf(" = ");
+		dump_sigspec(f, right.extract(offset, GetSize(chunk)));
+		f << stringf(";\n");
+		offset += GetSize(chunk);
+	}
 }
 
 void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw);