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| author | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
| commit | 83b2e0272333cfcc2529e0833723a52c066146a6 (patch) | |
| tree | 9985b7f840383419ebd5b189023ca6871a02d5a9 /backends/verilog/verilog_backend.cc | |
| parent | b8cd4ad64ae9a45faecffc1a6b92a8219755bc60 (diff) | |
| parent | fb568ddb4e2ccaab352d9d062f6b4926aca75680 (diff) | |
| download | yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.gz yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.bz2 yosys-83b2e0272333cfcc2529e0833723a52c066146a6.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0b3a6f80..776f4eacb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -558,6 +558,20 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$_NMUX_") { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = !("); + dump_cell_expr_port(f, cell, "S", false); + f << stringf(" ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "B", false); + f << stringf(" : "); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(");\n"); + return true; + } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); |