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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:17:09 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:17:09 -0800 |
commit | 8241db6960d17469678e8c71fd7d6c1b7ddc4fe7 (patch) | |
tree | 1e0404eedc4758fe6c90a6e7526a35dcc3e36628 /backends/verilog/verilog_backend.cc | |
parent | 742b4e01b498ae2e735d40565f43607d69a015d8 (diff) | |
download | yosys-8241db6960d17469678e8c71fd7d6c1b7ddc4fe7.tar.gz yosys-8241db6960d17469678e8c71fd7d6c1b7ddc4fe7.tar.bz2 yosys-8241db6960d17469678e8c71fd7d6c1b7ddc4fe7.zip |
write_verilog to cope with init attr on q when -noexpr
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
-rw-r--r-- | backends/verilog/verilog_backend.cc | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a7f329ef8..04191443a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1247,7 +1247,30 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_attributes(f, indent, cell->attributes); f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); - if (!defparam && cell->parameters.size() > 0) { + std::string init; + if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + auto q_wire = cell->getPort("\\Q"); + + Const initval; + bool gotinit = false; + + for (auto bit : active_sigmap(q_wire)) { + if (active_initdata.count(bit)) { + initval.bits.push_back(active_initdata.at(bit)); + gotinit = true; + } else { + initval.bits.push_back(State::Sx); + } + } + + if (gotinit) { + std::stringstream ss; + dump_const(ss, initval); + init = ss.str(); + } + } + + if (!defparam && (cell->parameters.size() > 0 || !init.empty())) { f << stringf(" #("); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { if (it != cell->parameters.begin()) @@ -1257,6 +1280,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(")"); } + if (!init.empty()) { + if (!cell->parameters.empty()) + f << stringf(","); + f << stringf("\n%s .INIT(%s)", indent.c_str(), init.c_str()); + } f << stringf("\n%s" ")", indent.c_str()); } @@ -1298,13 +1326,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } f << stringf("\n%s" ");\n", indent.c_str()); - if (defparam && cell->parameters.size() > 0) { + if (defparam && (cell->parameters.size() > 0 || !init.empty())) { for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str()); bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0; dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(";\n"); } + if (!init.empty()) + f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str()); } } |