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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-22 20:26:19 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-22 20:31:04 +0200 |
| commit | 5059b3166098044a87b3d0b7f3ae2957df7e6194 (patch) | |
| tree | 56354acd86f6a874e9054774587907ee8e7f3754 /backends/verilog/verilog_backend.cc | |
| parent | 39ee561169ba04374c2c630a5ef5a61537a67c13 (diff) | |
| download | yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.tar.gz yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.tar.bz2 yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.zip | |
Added simple xilinx7 technology mapping files
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions