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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-06 04:47:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-06 04:47:55 +0200 |
| commit | 023086bd46bc828621ebb171b159efe1398aaecf (patch) | |
| tree | e94e14733c13e234d5c5055082d732be26fd6d9b /backends/verilog/verilog_backend.cc | |
| parent | 44a9dcbbbf47f1a6f524c6328ff775f29573a935 (diff) | |
| download | yosys-023086bd46bc828621ebb171b159efe1398aaecf.tar.gz yosys-023086bd46bc828621ebb171b159efe1398aaecf.tar.bz2 yosys-023086bd46bc828621ebb171b159efe1398aaecf.zip | |
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0b3a6f80..776f4eacb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -558,6 +558,20 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$_NMUX_") { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = !("); + dump_cell_expr_port(f, cell, "S", false); + f << stringf(" ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "B", false); + f << stringf(" : "); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(");\n"); + return true; + } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); |