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| author | Clifford Wolf <clifford@clifford.at> | 2016-01-06 13:54:00 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-01-06 13:54:00 +0100 |
| commit | 1f8c47fb47e9d15808e66e423827598bb1050411 (patch) | |
| tree | 8971ba0333a746ef1f79a362228b58121bef1279 /backends/verilog/Makefile.inc | |
| parent | 1d62f8710f04fec405ef79b9e9a4a031afcf7d42 (diff) | |
| download | yosys-1f8c47fb47e9d15808e66e423827598bb1050411.tar.gz yosys-1f8c47fb47e9d15808e66e423827598bb1050411.tar.bz2 yosys-1f8c47fb47e9d15808e66e423827598bb1050411.zip | |
Added "equiv_add -try" mode
Diffstat (limited to 'backends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions