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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-19 21:37:40 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-19 21:37:40 +0200 |
| commit | 1277d1bcb8c325d1c7addafee9da90b521bc0da6 (patch) | |
| tree | 6eb2603522717a915ac08a04ade3dc44120285c7 /backends/verilog/Makefile.inc | |
| parent | 7ff802e199d231029f735a3e37bec508e0d840c5 (diff) | |
| download | yosys-1277d1bcb8c325d1c7addafee9da90b521bc0da6.tar.gz yosys-1277d1bcb8c325d1c7addafee9da90b521bc0da6.tar.bz2 yosys-1277d1bcb8c325d1c7addafee9da90b521bc0da6.zip | |
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
Diffstat (limited to 'backends/verilog/Makefile.inc')
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