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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 19:59:25 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 19:59:25 -0700 |
| commit | 116c2496011aeeac9847d69af597a0db58209793 (patch) | |
| tree | 3dd99df44d7cd1201c320990e34690f06929ffec /backends/verilog/Makefile.inc | |
| parent | 34ae29295db53289e786c0279ed00474cf0294d3 (diff) | |
| download | yosys-116c2496011aeeac9847d69af597a0db58209793.tar.gz yosys-116c2496011aeeac9847d69af597a0db58209793.tar.bz2 yosys-116c2496011aeeac9847d69af597a0db58209793.zip | |
-auto-top should check $abstract (deferred) modules with (* top *)
Diffstat (limited to 'backends/verilog/Makefile.inc')
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