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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-20 16:21:35 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-20 16:21:35 +0200 |
| commit | 060bf4819a3742ba2ad8142c9a7e665555c22ac7 (patch) | |
| tree | ce4033c346738807072ea2d5fad9ff9490aab490 /backends/spice | |
| parent | ffcdc53a18197e40571b9c604fff07408cc12346 (diff) | |
| download | yosys-060bf4819a3742ba2ad8142c9a7e665555c22ac7.tar.gz yosys-060bf4819a3742ba2ad8142c9a7e665555c22ac7.tar.bz2 yosys-060bf4819a3742ba2ad8142c9a7e665555c22ac7.zip | |
Small improvements in Verilog front-end docs
Diffstat (limited to 'backends/spice')
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