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| author | Vamsi K Vytla <vamsi.vytla@gmail.com> | 2020-04-27 09:44:24 -0700 |
|---|---|---|
| committer | Vamsi K Vytla <vamsi.vytla@gmail.com> | 2020-04-27 09:44:24 -0700 |
| commit | 5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c (patch) | |
| tree | 4a8694391c20cf6e6a8623f6e9fdc7c6daee3297 /backends/json | |
| parent | 3eb24809a1d80f4b7015e6f8b1458e300727c244 (diff) | |
| download | yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.tar.gz yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.tar.bz2 yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.zip | |
Preserve 'signed'-ness of a verilog wire through RTLIL
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
Diffstat (limited to 'backends/json')
| -rw-r--r-- | backends/json/json.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/json/json.cc b/backends/json/json.cc index 1a8b757ef..5edc50f60 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -160,6 +160,8 @@ struct JsonWriter f << stringf(" \"offset\": %d,\n", w->start_offset); if (w->upto) f << stringf(" \"upto\": 1,\n"); + if (w->is_signed) + f << stringf(" \"signed\": %d,\n", w->is_signed); f << stringf(" \"bits\": %s\n", get_bits(w).c_str()); f << stringf(" }"); first = false; @@ -227,6 +229,8 @@ struct JsonWriter f << stringf(" \"offset\": %d,\n", w->start_offset); if (w->upto) f << stringf(" \"upto\": 1,\n"); + if (w->is_signed) + f << stringf(" \"signed\": %d,\n", w->is_signed); f << stringf(" \"attributes\": {"); write_parameters(w->attributes); f << stringf("\n }\n"); |