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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
| commit | f9946232adf887e5aa4a48c64f88eaa17e424009 (patch) | |
| tree | 39594b3287c3369752668456c4a6b1735fb66e77 /backends/intersynth | |
| parent | d7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff) | |
| download | yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.gz yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.bz2 yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.zip | |
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'backends/intersynth')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8c08747c3..4e8c321bb 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -147,7 +147,7 @@ struct IntersynthBackend : public Backend { netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name)); // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input || wire->port_output) { celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n", |