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author | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:27:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:27:30 +0200 |
commit | e9dede01ca8834ea3c211862a5d6c0119b2b578a (patch) | |
tree | b4c2d02cefb1dce8976a222b34c7c8f53d7b4a84 /backends/intersynth | |
parent | 23cf23418cd28b98c11a1ed3fb45dbb927f48e65 (diff) | |
download | yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.tar.gz yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.tar.bz2 yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.zip |
Fixed handling of boolean attributes (backends)
Diffstat (limited to 'backends/intersynth')
-rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 513c17531..83db8908c 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend { RTLIL::Module *module = module_it.second; SigMap sigmap(module); - if (module->attributes.count("\\placeholder") > 0) + if (module->get_bool_attribute("\\placeholder")) continue; if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) continue; |