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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 15:07:46 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 15:07:46 -0800 |
| commit | 7d94e18100a6fe61805e94e754b199826571e7ef (patch) | |
| tree | 7de6e21cdb193fe1ca7c8d08b624511b2bcc8bf3 /backends/intersynth | |
| parent | 291530c59f639609bc7534e561f28c9fb4081e19 (diff) | |
| download | yosys-7d94e18100a6fe61805e94e754b199826571e7ef.tar.gz yosys-7d94e18100a6fe61805e94e754b199826571e7ef.tar.bz2 yosys-7d94e18100a6fe61805e94e754b199826571e7ef.zip | |
synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
Diffstat (limited to 'backends/intersynth')
0 files changed, 0 insertions, 0 deletions