Replace "ILANG" with "RTLIL" everywhere.

The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.

1 files changed, 2 insertions, 2 deletions

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 98a14173b..a6b36de6c 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -59,7 +59,7 @@ struct IntersynthBackend : public Backend {
 		log("        do not generate celltypes and conntypes commands. i.e. just output\n");
 		log("        the netlists. this is used for postsilicon synthesis.\n");
 		log("\n");
-		log("    -lib <verilog_or_ilang_file>\n");
+		log("    -lib <verilog_or_rtlil_file>\n");
 		log("        Use the specified library file for determining whether cell ports are\n");
 		log("        inputs or outputs. This option can be used multiple times to specify\n");
 		log("        more than one library.\n");
@@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend {
 			if (f.fail())
 				log_error("Can't open lib file `%s'.\n", filename.c_str());
 			RTLIL::Design *lib = new RTLIL::Design;
-			Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
+			Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
 			libs.push_back(lib);
 		}