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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 23:43:25 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-28 00:40:56 +0200 |
| commit | cbf6b719fe85ce8544f9bb0796711f3f45638862 (patch) | |
| tree | e5123705ba397f310a10c133d02fd4360c42800d /backends/firrtl/firrtl.cc | |
| parent | 055ba748bcf8c77bff15bda0de49c0b4b3722bba (diff) | |
| download | yosys-cbf6b719fe85ce8544f9bb0796711f3f45638862.tar.gz yosys-cbf6b719fe85ce8544f9bb0796711f3f45638862.tar.bz2 yosys-cbf6b719fe85ce8544f9bb0796711f3f45638862.zip | |
Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
Diffstat (limited to 'backends/firrtl/firrtl.cc')
| -rw-r--r-- | backends/firrtl/firrtl.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index dee24d0e2..86b1bbdf6 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -542,6 +542,8 @@ struct FirrtlWorker vector<string> port_decls, wire_decls, mem_exprs, cell_exprs, wire_exprs; std::vector<Mem> memories = Mem::get_all_memories(module); + for (auto &mem : memories) + mem.narrow(); for (auto wire : module->wires()) { @@ -993,8 +995,6 @@ struct FirrtlWorker if (port.clk_enable) log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); - if (port.wide_log2 != 0) - log_error("Wide read port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid)); std::ostringstream rpe; @@ -1016,8 +1016,6 @@ struct FirrtlWorker if (!port.clk_enable) log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); - if (port.wide_log2 != 0) - log_error("Wide write port %d on memory %s.%s. Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid)); if (!port.clk_polarity) log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); for (int i = 1; i < GetSize(port.en); i++) |