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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
| commit | 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 (patch) | |
| tree | 900ad3764a73cb81396bcf0c0be1bc92c4df135d /backends/firrtl/firrtl.cc | |
| parent | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (diff) | |
| download | yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.gz yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.bz2 yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.zip | |
Use State::S{0,1}
Diffstat (limited to 'backends/firrtl/firrtl.cc')
| -rw-r--r-- | backends/firrtl/firrtl.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 1c7a7351f..4758c6d4d 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -122,9 +122,9 @@ struct FirrtlWorker // Current (3/13/2019) conventions: // generate a constant 0 for clock and a constant 1 for enable if they are undefined. if (!clk.is_fully_def()) - this->clk = SigSpec(RTLIL::Const(0, 1)); + this->clk = SigSpec(State::S0); if (!ena.is_fully_def()) - this->ena = SigSpec(RTLIL::Const(1, 1)); + this->ena = SigSpec(State::S1); } string gen_read(const char * indent) { string addr_expr = make_expr(addr); |