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| author | whitequark <whitequark@whitequark.org> | 2020-12-13 00:54:12 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-12-13 15:33:55 +0000 |
| commit | ac1a78923af80cec3760cfbd0f6f4a96d180cce8 (patch) | |
| tree | e69d07ddb9d41e7489f5874dc2f1e960e97ec538 /backends/cxxrtl | |
| parent | 080f311040a0c1bb5fd877e4ad06fc613fdc3314 (diff) | |
| download | yosys-ac1a78923af80cec3760cfbd0f6f4a96d180cce8.tar.gz yosys-ac1a78923af80cec3760cfbd0f6f4a96d180cce8.tar.bz2 yosys-ac1a78923af80cec3760cfbd0f6f4a96d180cce8.zip | |
cxxrtl: use IdString::isPublic(). NFC.
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index c193d78e9..f1ed47541 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -211,7 +211,7 @@ bool is_ff_cell(RTLIL::IdString type) bool is_internal_cell(RTLIL::IdString type) { - return type[0] == '$' && !type.begins_with("$paramod"); + return !type.isPublic() && !type.begins_with("$paramod"); } bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell) @@ -1665,7 +1665,7 @@ struct CxxrtlWorker { inc_indent(); f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n"; for (auto wire : module->wires()) { - if (wire->name[0] != '\\') + if (!wire->name.isPublic()) continue; if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0)) continue; @@ -1743,7 +1743,7 @@ struct CxxrtlWorker { } if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto &memory_it : module->memories) { - if (memory_it.first[0] != '\\') + if (!memory_it.first.isPublic()) continue; f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second)); f << ", debug_item(" << mangle(memory_it.second) << ", "; @@ -2338,7 +2338,7 @@ struct CxxrtlWorker { // Note that the information collected here can't be used for optimizing the netlist: debug information queries // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold. for (auto wire : module->wires()) { - if (wire->name[0] != '\\') + if (!wire->name.isPublic()) continue; if (!unbuffered_wires[wire]) continue; |