diff options
| author | whitequark <whitequark@whitequark.org> | 2020-04-22 12:45:19 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-22 12:47:28 +0000 |
| commit | 93288b8eaea3e346275082352edeea5cfb4ac38a (patch) | |
| tree | 408110df9e052d06e6cd6eacb19eff80ec12d68e /backends/cxxrtl | |
| parent | 1d5b6ac253a397d173b92549d420d898f80e577f (diff) | |
| download | yosys-93288b8eaea3e346275082352edeea5cfb4ac38a.tar.gz yosys-93288b8eaea3e346275082352edeea5cfb4ac38a.tar.bz2 yosys-93288b8eaea3e346275082352edeea5cfb4ac38a.zip | |
cxxrtl: run edge detectors only once in eval().
As a result, Minerva SRAM SoC runs ~15% faster.
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index bb473cefb..237700b29 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -1020,7 +1020,7 @@ struct CxxrtlWorker { RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") - << mangle(clk_bit) << "()) {\n"; + << mangle(clk_bit) << ") {\n"; inc_indent(); if (cell->type == ID($dffe)) { f << indent << "if ("; @@ -1097,7 +1097,7 @@ struct CxxrtlWorker { RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") - << mangle(clk_bit) << "()) {\n"; + << mangle(clk_bit) << ") {\n"; inc_indent(); } RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; @@ -1365,16 +1365,16 @@ struct CxxrtlWorker { switch (sync->type) { case RTLIL::STp: log_assert(sync_bit.wire != nullptr); - events.insert("posedge_" + mangle(sync_bit) + "()"); + events.insert("posedge_" + mangle(sync_bit)); break; case RTLIL::STn: log_assert(sync_bit.wire != nullptr); - events.insert("negedge_" + mangle(sync_bit) + "()"); + events.insert("negedge_" + mangle(sync_bit)); break; case RTLIL::STe: log_assert(sync_bit.wire != nullptr); - events.insert("posedge_" + mangle(sync_bit) + "()"); - events.insert("negedge_" + mangle(sync_bit) + "()"); + events.insert("posedge_" + mangle(sync_bit)); + events.insert("negedge_" + mangle(sync_bit)); break; case RTLIL::STa: @@ -1522,6 +1522,22 @@ struct CxxrtlWorker { inc_indent(); f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n"; if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) { + for (auto wire : module->wires()) { + if (edge_wires[wire]) { + for (auto edge_type : edge_types) { + if (edge_type.first.wire == wire) { + if (edge_type.second != RTLIL::STn) { + f << indent << "bool posedge_" << mangle(edge_type.first) << " = "; + f << "this->posedge_" << mangle(edge_type.first) << "();\n"; + } + if (edge_type.second != RTLIL::STp) { + f << indent << "bool negedge_" << mangle(edge_type.first) << " = "; + f << "this->negedge_" << mangle(edge_type.first) << "();\n"; + } + } + } + } + } for (auto wire : module->wires()) dump_wire(wire, /*is_local_context=*/true); for (auto node : schedule[module]) { |