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| author | whitequark <whitequark@whitequark.org> | 2020-04-14 12:34:35 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-14 12:36:20 +0000 |
| commit | 0d0bf9c4a2acd70418670518bf641f7628c92165 (patch) | |
| tree | 8e1b8e2265368f8dedcb3aad577680b6f00078d8 /backends/cxxrtl | |
| parent | f44b287f8e36684607447beb05556f1a5a34d625 (diff) | |
| download | yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.tar.gz yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.tar.bz2 yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.zip | |
write_cxxrtl: ignore disconnected module ports.
E.g. port `q` in `submod x(.p(p), .q());`.
Fixes #1920.
Diffstat (limited to 'backends/cxxrtl')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index 465882858..6038f87b1 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -970,6 +970,8 @@ struct CxxrtlWorker { continue; } if (cell->output(conn.first)) { + if (conn.second.empty()) + continue; // ignore disconnected ports f << indent; dump_sigspec_lhs(conn.second); f << " = " << mangle(cell) << "." << mangle_wire_name(conn.first) << ".curr;\n"; |