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| author | Ethan Mahintorabi <ethanmoon@google.com> | 2022-08-24 00:32:33 +0000 |
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| committer | Ethan Mahintorabi <ethanmoon@google.com> | 2022-08-24 00:35:02 +0000 |
| commit | 114253cd54808d929022014928eff9cd5eb0f275 (patch) | |
| tree | bcb8ea360c7474ad0c509719abe2203e1de3eed2 /backends/cxxrtl/cxxrtl_vcd.h | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| download | yosys-114253cd54808d929022014928eff9cd5eb0f275.tar.gz yosys-114253cd54808d929022014928eff9cd5eb0f275.tar.bz2 yosys-114253cd54808d929022014928eff9cd5eb0f275.zip | |
Improves ABC command runtime by 10-100x
After speaking with the author of ABC he let me know that ifraig is a very old command, and that &get; &fraig -x; &put is over 100x faster than ifraig with improved PPA results.
After making the change I confirmed that this is in fact a major speed up. On our internal designs in O(millions) of standard cells we saw multi hour reductions in runtime.
Also included is an improvement to the dress command. Using AIG based transformations removes the spec it SATs against. Proving the input blif will make sure that no matter what commands are run the dress command can still do its job. I noticed a regression against some LUT mapping jobs that prompted me to fix this.
Diffstat (limited to 'backends/cxxrtl/cxxrtl_vcd.h')
0 files changed, 0 insertions, 0 deletions