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authorwhitequark <whitequark@whitequark.org>2020-12-21 02:15:55 +0000
committerwhitequark <whitequark@whitequark.org>2020-12-21 02:20:34 +0000
commitb9721bedf01ca1f536bbf13ba761333c6867bd29 (patch)
tree5a262c642e0f07230fc81cc7a1a39344603a77a3 /backends/cxxrtl/cxxrtl_backend.cc
parent40ca9d038b1e657b9b9ac17e7e5a2969c9922e00 (diff)
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cxxrtl: speed up bit repeats (sign extends, etc).
On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
Diffstat (limited to 'backends/cxxrtl/cxxrtl_backend.cc')
-rw-r--r--backends/cxxrtl/cxxrtl_backend.cc25
1 files changed, 20 insertions, 5 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 3b2fb4985..916303bfe 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -832,11 +832,26 @@ struct CxxrtlWorker {
} else if (sig.is_chunk()) {
return dump_sigchunk(sig.as_chunk(), is_lhs, for_debug);
} else {
- dump_sigchunk(*sig.chunks().rbegin(), is_lhs, for_debug);
- for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) {
- f << ".concat(";
- dump_sigchunk(*it, is_lhs, for_debug);
- f << ")";
+ bool first = true;
+ auto chunks = sig.chunks();
+ for (auto it = chunks.rbegin(); it != chunks.rend(); it++) {
+ if (!first)
+ f << ".concat(";
+ bool is_complex = dump_sigchunk(*it, is_lhs, for_debug);
+ if (!is_lhs && it->width == 1) {
+ size_t repeat = 1;
+ while ((it + repeat) != chunks.rend() && *(it + repeat) == *it)
+ repeat++;
+ if (repeat > 1) {
+ if (is_complex)
+ f << ".val()";
+ f << ".repeat<" << repeat << ">()";
+ }
+ it += repeat - 1;
+ }
+ if (!first)
+ f << ")";
+ first = false;
}
return true;
}