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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 17:50:59 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 23:47:42 +0200 |
| commit | 055ba748bcf8c77bff15bda0de49c0b4b3722bba (patch) | |
| tree | db1658fdd2f0dac471b61adb4fec55185935e619 /backends/btor/btor.cc | |
| parent | aabe1c382e635040d16b6a29c7e2741e8e9d7adf (diff) | |
| download | yosys-055ba748bcf8c77bff15bda0de49c0b4b3722bba.tar.gz yosys-055ba748bcf8c77bff15bda0de49c0b4b3722bba.tar.bz2 yosys-055ba748bcf8c77bff15bda0de49c0b4b3722bba.zip | |
backends/verilog: Add support for memory read port reset and init value.
Diffstat (limited to 'backends/btor/btor.cc')
0 files changed, 0 insertions, 0 deletions