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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
| commit | 71649969213863b2695f1c51956886fc7879c3e6 (patch) | |
| tree | 7fb2cf4be9d2d5628dc4c54a8c9161fd57e62bfd /backends/blif/blif.cc | |
| parent | e6d5147214bd157c457654dc46547775ec6ad324 (diff) | |
| download | yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.gz yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.bz2 yosys-71649969213863b2695f1c51956886fc7879c3e6.zip | |
RTLIL::S{0,1} -> State::S{0,1}
Diffstat (limited to 'backends/blif/blif.cc')
| -rw-r--r-- | backends/blif/blif.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index f32b0f533..b6e38c16c 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -377,7 +377,7 @@ struct BlifDumper f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); for (int i = 0; i < (1 << width); i++) - if (mask[i] == RTLIL::S1) { + if (mask[i] == State::S1) { for (int j = width-1; j >= 0; j--) { f << ((i>>j)&1 ? '1' : '0'); } |