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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /backends/aiger | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/aiger.cc | 24 | ||||
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
2 files changed, 17 insertions, 17 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index a51e3648c..25f584f95 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -171,8 +171,8 @@ struct AigerWriter { if (cell->type == "$_NOT_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -191,9 +191,9 @@ struct AigerWriter if (cell->type == "$_AND_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -203,7 +203,7 @@ struct AigerWriter if (cell->type == "$initstate") { - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); undriven_bits.erase(Y); initstate_bits.insert(Y); continue; @@ -211,7 +211,7 @@ struct AigerWriter if (cell->type == "$assert") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -221,7 +221,7 @@ struct AigerWriter if (cell->type == "$assume") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -231,7 +231,7 @@ struct AigerWriter if (cell->type == "$live") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -241,7 +241,7 @@ struct AigerWriter if (cell->type == "$fair") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -251,7 +251,7 @@ struct AigerWriter if (cell->type == "$anyconst") { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); ff_map[bit] = bit; } @@ -260,7 +260,7 @@ struct AigerWriter if (cell->type == "$anyseq") { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); input_bits.insert(bit); } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde6d066a..fe1a6446b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -192,8 +192,8 @@ struct XAigerWriter if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -202,9 +202,9 @@ struct XAigerWriter if (cell->type == "$_AND_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); |