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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:44:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:44:30 -0700 |
| commit | fb2758aade4561d8c379e8b9d97ee871b1bbfde3 (patch) | |
| tree | ef5e8b6964937ddaa8397208cd29f191c2515b44 /backends/aiger | |
| parent | 2e7b3eee400a4d845398be8e15ca023672f05270 (diff) | |
| download | yosys-fb2758aade4561d8c379e8b9d97ee871b1bbfde3.tar.gz yosys-fb2758aade4561d8c379e8b9d97ee871b1bbfde3.tar.bz2 yosys-fb2758aade4561d8c379e8b9d97ee871b1bbfde3.zip | |
write_xaiger to preserve POs even if driven by constant
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3dbff5496..3a4b353e2 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -142,8 +142,10 @@ struct XAigerWriter SigBit wirebit(wire, i); SigBit bit = sigmap(wirebit); - undriven_bits.insert(bit); - unused_bits.insert(bit); + if (bit.wire) { + undriven_bits.insert(bit); + unused_bits.insert(bit); + } if (wire->port_input || keep) { if (bit != wirebit) @@ -154,7 +156,8 @@ struct XAigerWriter if (wire->port_output || keep) { if (bit != wirebit) { alias_map[wirebit] = bit; - undriven_bits.insert(wirebit); + if (!bit.wire) + undriven_bits.insert(wirebit); } output_bits.insert(wirebit); } @@ -480,10 +483,6 @@ struct XAigerWriter } } - // Erase all POs that are undriven - if (!holes_mode) - for (auto bit : undriven_bits) - output_bits.erase(bit); for (auto bit : unused_bits) undriven_bits.erase(bit); |