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author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 16:04:19 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:34:09 -0800 |
commit | f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15 (patch) | |
tree | bfb9641ea7b4a3b6fbfb9c3d06ad2facc958acc4 /backends/aiger | |
parent | 00d41905df74fd8bbfc5950c4c1ecf2d38394eaf (diff) | |
download | yosys-f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.tar.gz yosys-f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.tar.bz2 yosys-f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.zip |
abc9: fix abc9_arrival for flops
Diffstat (limited to 'backends/aiger')
-rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 76b7efbfc..4149a8628 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -643,7 +643,6 @@ struct XAigerWriter write_s_buffer(ff_bits.size()); for (const auto &i : ff_bits) { - const SigBit &d = i.first; const Cell *cell = i.second; int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int(); @@ -661,7 +660,11 @@ struct XAigerWriter write_s_buffer(0); } - write_i_buffer(arrival_times.at(d, 0)); + auto it = cell->attributes.find(ID(abc9_arrival)); + if (it != cell->attributes.end()) + write_i_buffer(it->second.as_int()); + else + write_i_buffer(0); //write_o_buffer(0); } |