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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 12:26:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 12:26:51 -0700 |
| commit | e3c8132d7acaae328adeb8d4db1857275b5e8323 (patch) | |
| tree | ffd5bb9607174576f86cb522f555347dc8e2eaa8 /backends/aiger | |
| parent | c6fa4faa371ad3dbefe4c57bd758942e461869da (diff) | |
| download | yosys-e3c8132d7acaae328adeb8d4db1857275b5e8323.tar.gz yosys-e3c8132d7acaae328adeb8d4db1857275b5e8323.tar.bz2 yosys-e3c8132d7acaae328adeb8d4db1857275b5e8323.zip | |
Do not re-sort box_module ports
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 25de7daba..efdd1844b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -739,10 +739,12 @@ struct XAigerWriter if (box_module->get_bool_attribute("\\whitebox")) holes_cell = holes_module->addCell(cell->name, cell->type); - RTLIL::Wire *holes_wire; - // TODO: Only sort once - box_module->wires_.sort(RTLIL::sort_by_id_str()); - for (const auto w : box_module->wires()) { + // NB: Assume box_module->ports are sorted alphabetically + // (as RTLIL::Module::fixup_ports() would do) + for (const auto &port_name : box_module->ports) { + RTLIL::Wire *w = box_module->wire(port_name); + log_assert(w); + RTLIL::Wire *holes_wire; RTLIL::SigSpec port_wire; if (w->port_input) { for (int i = 0; i < GetSize(w); i++) { |