WIP

1 files changed, 141 insertions, 23 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 42a26cbf9..02ab47ac0 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -619,26 +619,90 @@ struct XAigerWriter
 		//	write_o_buffer(0);
 
 		if (!box_list.empty() || !ff_bits.empty()) {
+			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
+			log_assert(holes_module);
+
+			dict<IdString, Cell*> cell_cache;
+
+			int port_id = 1;
 			int box_count = 0;
 			for (auto cell : box_list) {
 				RTLIL::Module* orig_box_module = module->design->module(cell->type);
 				log_assert(orig_box_module);
 				IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
 				RTLIL::Module* box_module = module->design->module(derived_name);
+				if (box_module->has_processes())
+					Pass::call_on_module(module->design, box_module, "proc");
+
+				auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
+				Cell *holes_cell = r.first->second;
+				if (r.second && box_module->get_bool_attribute("\\whitebox")) {
+					holes_cell = holes_module->addCell(cell->name, cell->type);
+					holes_cell->parameters = cell->parameters;
+					r.first->second = holes_cell;
+				}
 
 				int box_inputs = 0, box_outputs = 0;
 				for (auto port_name : box_ports.at(cell->type)) {
 					RTLIL::Wire *w = box_module->wire(port_name);
 					log_assert(w);
+					RTLIL::Wire *holes_wire;
+					RTLIL::SigSpec port_sig;
+
 					if (w->port_input)
-						box_inputs += GetSize(w);
-					if (w->port_output)
+						for (int i = 0; i < GetSize(w); i++) {
+							box_inputs++;
+							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+							if (!holes_wire) {
+								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+								holes_wire->port_input = true;
+								holes_wire->port_id = port_id++;
+								holes_module->ports.push_back(holes_wire->name);
+							}
+							if (holes_cell)
+								port_sig.append(holes_wire);
+						}
+					if (w->port_output) {
 						box_outputs += GetSize(w);
+						for (int i = 0; i < GetSize(w); i++) {
+							if (GetSize(w) == 1)
+								holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
+							else
+								holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
+							holes_wire->port_output = true;
+							holes_wire->port_id = port_id++;
+							holes_module->ports.push_back(holes_wire->name);
+							if (holes_cell)
+								port_sig.append(holes_wire);
+							else
+								holes_module->connect(holes_wire, State::S0);
+						}
+					}
+					if (!port_sig.empty()) {
+						if (r.second)
+							holes_cell->setPort(w->name, port_sig);
+						else
+							holes_module->connect(holes_cell->getPort(w->name), port_sig);
+					}
 				}
 
-				// For flops only, create an extra 1-bit input for abc9_ff.Q
-				if (box_module->get_bool_attribute("\\abc9_flop"))
+				// For flops only, create an extra 1-bit input that drives a new wire
+				//   called "<cell>.abc9_ff.Q" that is used below
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
+					log_assert(holes_cell);
+
 					box_inputs++;
+					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+					if (!holes_wire) {
+						holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+						holes_wire->port_input = true;
+						holes_wire->port_id = port_id++;
+						holes_module->ports.push_back(holes_wire->name);
+					}
+					Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
+					log_assert(w);
+					holes_module->connect(w, holes_wire);
+				}
 
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
@@ -690,27 +754,81 @@ struct XAigerWriter
 			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 			f.write(buffer_str.data(), buffer_str.size());
 
-			RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
-			log_assert(holes_module);
-
-			for (auto cell : holes_module->cells())
-				if (!cell->type.in("$_NOT_", "$_AND_"))
-					log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
-
-			module->design->selection_stack.emplace_back(false);
-			module->design->selection().select(holes_module);
-
-			std::stringstream a_buffer;
-			XAigerWriter writer(holes_module);
-			writer.write_aiger(a_buffer, false /*ascii_mode*/);
+			if (holes_module) {
+				log_push();
+
+				// NB: fixup_ports() will sort ports by name
+				//holes_module->fixup_ports();
+				holes_module->check();
+
+				// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
+				//   since boxes may contain parameters in which case `flatten` would have
+				//   created a new $paramod ...
+				Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
+
+				dict<SigSig, SigSig> replace;
+				for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
+					auto cell = it->second;
+					if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
+								"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
+						SigBit D = cell->getPort("\\D");
+						SigBit Q = cell->getPort("\\Q");
+						// Remove the DFF cell from what needs to be a combinatorial box
+						it = holes_module->cells_.erase(it);
+						Wire *port;
+						if (GetSize(Q.wire) == 1)
+							port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
+						else
+							port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
+						log_assert(port);
+						// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
+						//   in order to extract the combinatorial control logic that feeds the box
+						//   (i.e. clock enable, synchronous reset, etc.)
+						replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
+						// Since `flatten` above would have created wires named "<cell>.Q",
+						//   extract the pre-techmap cell name
+						auto pos = Q.wire->name.str().rfind(".");
+						log_assert(pos != std::string::npos);
+						IdString driver = Q.wire->name.substr(0, pos);
+						// And drive the signal that was previously driven by "DFF.Q" (typically
+						//   used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
+						//   wire (which itself is driven an input port) we inserted above
+						Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
+						log_assert(currQ);
+						holes_module->connect(Q, currQ);
+						continue;
+					}
+					else if (!cell->type.in("$_NOT_", "$_AND_"))
+						log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
+					++it;
+				}
 
-			module->design->selection_stack.pop_back();
+				for (auto &conn : holes_module->connections_) {
+					auto it = replace.find(conn);
+					if (it != replace.end())
+						conn = it->second;
+				}
 
-			f << "a";
-			buffer_str = a_buffer.str();
-			buffer_size_be = to_big_endian(buffer_str.size());
-			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
-			f.write(buffer_str.data(), buffer_str.size());
+				// Move into a new (temporary) design so that "clean" will only
+				// operate (and run checks on) this one module
+				RTLIL::Design *holes_design = new RTLIL::Design;
+				module->design->modules_.erase(holes_module->name);
+				holes_design->add(holes_module);
+				Pass::call(holes_design, "opt -purge");
+
+				std::stringstream a_buffer;
+				XAigerWriter writer(holes_module);
+				writer.write_aiger(a_buffer, false /*ascii_mode*/);
+				delete holes_design;
+
+				f << "a";
+				std::string buffer_str = a_buffer.str();
+				int32_t buffer_size_be = to_big_endian(buffer_str.size());
+				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+				f.write(buffer_str.data(), buffer_str.size());
+
+				log_pop();
+			}
 		}
 
 		f << "h";