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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-02 09:55:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-02 10:00:32 -0700 |
| commit | a0afa1787e71fca1fb143a96580136f4bf355251 (patch) | |
| tree | 74c88d8a139e2328b64dba4676deab114d92d30a /backends/aiger | |
| parent | ca3fc3c882b9a454c48bee7d701fa5cb254ae671 (diff) | |
| download | yosys-a0afa1787e71fca1fb143a96580136f4bf355251.tar.gz yosys-a0afa1787e71fca1fb143a96580136f4bf355251.tar.bz2 yosys-a0afa1787e71fca1fb143a96580136f4bf355251.zip | |
aiger: fixes for ports that have start_offset != 0
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/aiger.cc | 12 | ||||
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
2 files changed, 8 insertions, 9 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index cac32a8da..e5a41b5c5 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -629,30 +629,30 @@ struct AigerWriter int a = aig_map.at(sig[i]); if (verbose_map) - wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire)); + wire_lines[a] += stringf("wire %d %d %s\n", a, wire->start_offset+i, log_id(wire)); if (wire->port_input) { log_assert((a & 1) == 0); - input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); + input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire)); } if (wire->port_output) { int o = ordered_outputs.at(sig[i]); - output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); + output_lines[o] += stringf("output %d %d %s\n", o, wire->start_offset+i, log_id(wire)); } if (init_inputs.count(sig[i])) { int a = init_inputs.at(sig[i]); log_assert((a & 1) == 0); - init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire)); + init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire)); } if (ordered_latches.count(sig[i])) { int l = ordered_latches.at(sig[i]); if (zinit_mode && (aig_latchinit.at(l) == 1)) - latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire)); + latch_lines[l] += stringf("invlatch %d %d %s\n", l, wire->start_offset+i, log_id(wire)); else - latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire)); + latch_lines[l] += stringf("latch %d %d %s\n", l, wire->start_offset+i, log_id(wire)); } } } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3c7c745fe..1fb7210cb 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -725,13 +725,12 @@ struct XAigerWriter if (input_bits.count(b)) { int a = aig_map.at(b); log_assert((a & 1) == 0); - input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); + input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire)); } if (output_bits.count(b)) { int o = ordered_outputs.at(b); - int init = 2; - output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init); + output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire)); continue; } } |