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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:40:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:41:27 -0700 |
| commit | 8e56cfb6bbaa4e61b201c123b04a4eb4ca3403cf (patch) | |
| tree | 4579b79c836d50c41cd3c64c2c6ceda63dbc1bfb /backends/aiger | |
| parent | 0e97e6a00dfda0b4755599d4decdafb545e07aaa (diff) | |
| download | yosys-8e56cfb6bbaa4e61b201c123b04a4eb4ca3403cf.tar.gz yosys-8e56cfb6bbaa4e61b201c123b04a4eb4ca3403cf.tar.bz2 yosys-8e56cfb6bbaa4e61b201c123b04a4eb4ca3403cf.zip | |
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 55a95d835..82f0f24b2 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -104,8 +104,10 @@ struct XAigerWriter aig_map[bit] = bit2aig(alias_map.at(bit)); } - if (bit == State::Sx || bit == State::Sz) - log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n"); + if (bit == State::Sx || bit == State::Sz) { + log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); + aig_map[bit] = 0; + } } log_assert(aig_map.at(bit) >= 0); |