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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 16:44:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 16:44:35 -0700 |
| commit | 67fc0c3698693f049e805211c49d6219f17d7c7d (patch) | |
| tree | 9982fbc8c5feeb8469c4106c9de2ef85fedba453 /backends/aiger | |
| parent | 02df0198b65a2514d1343eeff8827f4e2cf858d0 (diff) | |
| download | yosys-67fc0c3698693f049e805211c49d6219f17d7c7d.tar.gz yosys-67fc0c3698693f049e805211c49d6219f17d7c7d.tar.bz2 yosys-67fc0c3698693f049e805211c49d6219f17d7c7d.zip | |
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3aa0e1110..69797ceaf 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -177,12 +177,12 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - bool scc = wire->attributes.count(ID::abc9_scc); - if (wire->port_input || scc) + bool keep = wire->get_bool_attribute(ID::abc9_keep); + if (wire->port_input || keep) input_bits.insert(bit); - bool keep = wire->get_bool_attribute(ID::keep); - if (wire->port_output || keep || scc) { + keep = keep || wire->get_bool_attribute(ID::keep); + if (wire->port_output || keep) { if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); @@ -225,7 +225,7 @@ struct XAigerWriter continue; } - if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) + if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) { SigBit D = sigmap(cell->getPort(ID::D).as_bit()); SigBit Q = sigmap(cell->getPort(ID::Q).as_bit()); |