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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:24:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:24:54 -0700 |
| commit | 61ca83e099ce9b08b0dcbfaac65a2e2870d58413 (patch) | |
| tree | 7daabe0f6a38baa173ac6d12d37c670e5d09043d /backends/aiger | |
| parent | aece97024de574fd765e18e31f685e9ffb0a13c6 (diff) | |
| download | yosys-61ca83e099ce9b08b0dcbfaac65a2e2870d58413.tar.gz yosys-61ca83e099ce9b08b0dcbfaac65a2e2870d58413.tar.bz2 yosys-61ca83e099ce9b08b0dcbfaac65a2e2870d58413.zip | |
Remove write_verilog call
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bd7347a19..99ca4f8d5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -630,7 +630,7 @@ struct XAigerWriter RTLIL::Selection& sel = holes_module->design->selection_stack.back(); sel.select(holes_module); - Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v"); + Pass::call(holes_module->design, "flatten; aigmap"); holes_module->design->selection_stack.pop_back(); |