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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 18:24:04 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 18:24:04 -0700 |
commit | 0debea25a731d83449b08152c7c6158e37e63d75 (patch) | |
tree | 1f6a7843179b1ee530ab6615129f9b7966b57915 /backends/aiger | |
parent | cdfb634977b3ee005c5635f7902ea21dd45f7311 (diff) | |
download | yosys-0debea25a731d83449b08152c7c6158e37e63d75.tar.gz yosys-0debea25a731d83449b08152c7c6158e37e63d75.tar.bz2 yosys-0debea25a731d83449b08152c7c6158e37e63d75.zip |
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Diffstat (limited to 'backends/aiger')
-rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c3a4e69c2..ce2f6e571 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -224,7 +224,7 @@ struct XAigerWriter // FIXME: Should short here, rather than provide $__ABC_FF_ // to ABC like a user cell - //if (cell->type.in("$_FF_" /*, "$_DFF_N_", "$_DFF_P_"*/)) + //if (cell->type == "$__ABC_FF_") //{ // SigBit D = sigmap(cell->getPort("\\D").as_bit()); // SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); |