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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 14:35:35 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 14:35:35 -0800 |
| commit | 78c0246d4abbd290289ed55a0008968293119446 (patch) | |
| tree | f1d5d81082cbd696349bf3ea92d66206ce2dca02 /backends/aiger/xaiger.cc | |
| parent | 6c340112fee1bb8989cbd41923aaa627d77d5110 (diff) | |
| download | yosys-78c0246d4abbd290289ed55a0008968293119446.tar.gz yosys-78c0246d4abbd290289ed55a0008968293119446.tar.bz2 yosys-78c0246d4abbd290289ed55a0008968293119446.zip | |
Revert "write_xaiger: use sigmap bits more consistently"
This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cff3183c1..c080cca4d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -294,7 +294,7 @@ struct XAigerWriter output_bits.insert(b); if (!cell_known) - inout_bits.insert(I); + inout_bits.insert(b); } } } @@ -315,7 +315,7 @@ struct XAigerWriter SigBit O = sigmap(b); if (O != b) alias_map[O] = b; - input_bits.insert(O); + input_bits.insert(b); if (arrival) arrival_times[b] = arrival; @@ -542,8 +542,9 @@ struct XAigerWriter undriven_bits.erase(bit); } - // For inout ports, or keep-ed wires, which end up being both a PI and a - // a PO then replace the PO with a new wire with the $inout.out suffix + // For inout ports, or keep-ed wires, then create a new wire with an + // $inout.out suffix, make it a PO driven by the existing inout, and + // inherit existing inout's drivers for (auto bit : inout_bits) { RTLIL::Wire *wire = bit.wire; RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); |