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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:42:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 21:57:50 -0800 |
| commit | 68717dd03b5a0bfff470cfbc004a43dd431f9236 (patch) | |
| tree | 58800b9e8b095b3397245cf342532e100397d4a9 /backends/aiger/xaiger.cc | |
| parent | 7136cee6b448cbe5478fd83ee1ca3eaa9f85eeb9 (diff) | |
| download | yosys-68717dd03b5a0bfff470cfbc004a43dd431f9236.tar.gz yosys-68717dd03b5a0bfff470cfbc004a43dd431f9236.tar.bz2 yosys-68717dd03b5a0bfff470cfbc004a43dd431f9236.zip | |
Do not sigmap keep bits inside write_xaiger
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 85136118a..97fec9376 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -168,7 +168,7 @@ struct XAigerWriter } if (keep) - keep_bits.insert(bit); + keep_bits.insert(wirebit); if (wire->port_input || keep) { if (bit != wirebit) |