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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 21:05:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 21:05:44 -0700 |
| commit | 5c134980c4d0f5c1f961d50c9c1fe1752d966e48 (patch) | |
| tree | 764005467742c8ca3d23a7ce28fe93c6e1215e2d /backends/aiger/xaiger.cc | |
| parent | 743c164eee06abb44601e00304db18cdb36a180f (diff) | |
| download | yosys-5c134980c4d0f5c1f961d50c9c1fe1752d966e48.tar.gz yosys-5c134980c4d0f5c1f961d50c9c1fe1752d966e48.tar.bz2 yosys-5c134980c4d0f5c1f961d50c9c1fe1752d966e48.zip | |
Optimise
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ce93ffb28..06496dbc3 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -585,18 +585,17 @@ struct XAigerWriter if (holes_module && !holes_module->cell(stringf("\\u%d", box_id))) holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type); RTLIL::Wire *holes_wire; - int num_inputs = 0; // NB: cell->connections_ already sorted from before for (const auto &c : cell->connections()) { + log_assert(c.second.size() == 1); if (cell->input(c.first)) { box_inputs += c.second.size(); if (holes_cell) { - holes_wire = holes_module->wire(stringf("\\i%d", num_inputs)); + holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); if (!holes_wire) { - holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs)); + holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); holes_wire->port_input = true; } - ++num_inputs; holes_cell->setPort(c.first, holes_wire); } } |