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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 22:22:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 22:22:17 -0800 |
| commit | 30f1204721ed592256ddde04f22dd40888b9e27c (patch) | |
| tree | 8c1721563973bc8bab3e6a3b2d77fa7a9b451493 /backends/aiger/xaiger.cc | |
| parent | f60cd4ff9b158a5d8ec51bd52b14f117214c087e (diff) | |
| download | yosys-30f1204721ed592256ddde04f22dd40888b9e27c.tar.gz yosys-30f1204721ed592256ddde04f22dd40888b9e27c.tar.bz2 yosys-30f1204721ed592256ddde04f22dd40888b9e27c.zip | |
Cleanup
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ae296d395..d4686736d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -521,7 +521,7 @@ struct XAigerWriter for (int i = 0; i < GetSize(wire); i++) { - if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr) + if (aig_map.count(sig[i]) == 0 /*|| sig[i].wire == nullptr*/) continue; int a = aig_map.at(sig[i]); @@ -529,13 +529,14 @@ struct XAigerWriter if (verbose_map) wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire)); - if (wire->port_input || ci_bits.count(RTLIL::SigBit{wire, i})) { + RTLIL::SigBit b(wire, i); + if (wire->port_input || ci_bits.count(b)) { log_assert((a & 1) == 0); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); } - if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) { - int o = ordered_outputs.at(sig[i]); + if (output_bits.count(b) || co_bits.count(b)) { + int o = ordered_outputs.at(b); output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); } |