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authorEddie Hung <eddie@fpgeh.com>2019-04-17 12:28:19 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-17 12:28:19 -0700
commit2b860809e9dae557a435f01a3125e6dd4b4a8599 (patch)
tree371d878ca2ac68240331229ccdc5469358273d46 /backends/aiger/xaiger.cc
parent58847df1b94d2caaa1fe959acb04425397f3567f (diff)
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Stop topological sort at abc_flop_q
Diffstat (limited to 'backends/aiger/xaiger.cc')
-rw-r--r--backends/aiger/xaiger.cc20
1 files changed, 13 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ed0fc656f..070d6d403 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -180,14 +180,20 @@ struct XAigerWriter
toposort.node(cell->name);
for (const auto &conn : cell->connections())
{
- // HACK!!!
- if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
- continue;
+ if (!cell->type.in("$_NOT_", "$_AND_")) {
+ if (yosys_celltypes.cell_known(cell->type)) {
+ if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+ continue;
+ if (cell->type == "$memrd" && conn.first == "\\DATA")
+ continue;
+ }
- if (yosys_celltypes.cell_known(cell->type)) {
- if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
- continue;
- if (cell->type == "$memrd" && conn.first == "\\DATA")
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ log_assert(inst_module);
+ RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+ log_assert(inst_module_port);
+
+ if (inst_module_port->attributes.count("\\abc_flop_q"))
continue;
}