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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 14:43:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 14:43:45 -0700 |
| commit | 1ec5f18346dd3f50e2340f4b79239a045ce7dd72 (patch) | |
| tree | 250609625e15cd0769013114f20c9697e5c3720d /backends/aiger/xaiger.cc | |
| parent | 437fec0d88b4a2ad172edf0d1a861a38845f3b1d (diff) | |
| download | yosys-1ec5f18346dd3f50e2340f4b79239a045ce7dd72.tar.gz yosys-1ec5f18346dd3f50e2340f4b79239a045ce7dd72.tar.bz2 yosys-1ec5f18346dd3f50e2340f4b79239a045ce7dd72.zip | |
Cope with inout ports
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 070d6d403..14fa4fb7f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -197,9 +197,12 @@ struct XAigerWriter continue; } - if (cell->input(conn.first)) + if (cell->input(conn.first)) { + // Ignore inout for the sake of topographical ordering + if (cell->output(conn.first)) continue; for (auto bit : sigmap(conn.second)) bit_users[bit].insert(cell->name); + } if (cell->output(conn.first)) for (auto bit : sigmap(conn.second)) @@ -287,7 +290,18 @@ struct XAigerWriter for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); +#ifndef NDEBUG + toposort.analyze_loops = true; +#endif toposort.sort(); +#ifndef NDEBUG + for (auto &it : toposort.loops) { + log(" loop"); + for (auto cell : it) + log(" %s", log_id(cell)); + log("\n"); + } +#endif log_assert(!toposort.found_loops); for (auto cell_name : toposort.sorted) { |