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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 15:32:58 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 15:32:58 -0800 |
| commit | 07feedfa736637952663dd8174123ea3bf1dddbc (patch) | |
| tree | 29915689d47bca1c9926825f0a840476754c9566 /backends/aiger/xaiger.cc | |
| parent | 6e866030c286d70f6ccff805e58b1fdd9a1a322b (diff) | |
| download | yosys-07feedfa736637952663dd8174123ea3bf1dddbc.tar.gz yosys-07feedfa736637952663dd8174123ea3bf1dddbc.tar.bz2 yosys-07feedfa736637952663dd8174123ea3bf1dddbc.zip | |
write_xaiger: get rid of external_bits dict
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 053f9d835..2b456bb9a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -78,7 +78,7 @@ struct XAigerWriter Module *module; SigMap sigmap; - pool<SigBit> input_bits, output_bits, external_bits; + pool<SigBit> input_bits, output_bits; dict<SigBit, SigBit> not_map, alias_map; dict<SigBit, pair<SigBit, SigBit>> and_map; vector<SigBit> ci_bits, co_bits; |