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author | Clifford Wolf <clifford@clifford.at> | 2017-07-03 14:53:17 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-07-03 14:53:17 +0200 |
commit | 287831dca36b1098165abd2381b35f81b2c0e312 (patch) | |
tree | 11b4fde54c54cfdc83e4339e11c79d0a03cfa692 /backends/aiger/aiger.cc | |
parent | ea805af6f53214a04d3fbae4b4906460cf16d87d (diff) | |
download | yosys-287831dca36b1098165abd2381b35f81b2c0e312.tar.gz yosys-287831dca36b1098165abd2381b35f81b2c0e312.tar.bz2 yosys-287831dca36b1098165abd2381b35f81b2c0e312.zip |
Include output ports with constant driver in AIGER output
Diffstat (limited to 'backends/aiger/aiger.cc')
-rw-r--r-- | backends/aiger/aiger.cc | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 5bf5a4c58..de0509930 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -112,10 +112,20 @@ struct AigerWriter init_map[initsig[i]] = initval[i] == State::S1; } + int index = 0; for (auto bit : sigmap(wire)) { if (bit.wire == nullptr) + { + if (wire->port_output) { + SigBit wirebit(wire, index); + aig_map[wirebit] = (bit == State::S1) ? 1 : 0; + output_bits.insert(wirebit); + } + + index++; continue; + } undriven_bits.insert(bit); unused_bits.insert(bit); @@ -125,6 +135,8 @@ struct AigerWriter if (wire->port_output) output_bits.insert(bit); + + index++; } } @@ -495,8 +507,12 @@ struct AigerWriter for (int i = 0; i < GetSize(wire); i++) { - if (sig[i].wire == nullptr) - continue; + if (sig[i].wire == nullptr) { + if (wire->port_output) + sig[i] = SigBit(wire, i); + else + continue; + } if (wire->port_input) { int a = aig_map.at(sig[i]); |