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authorAndrew Zonenberg <azonenberg@drawersteak.com>2016-12-12 17:05:06 +0800
committerAndrew Zonenberg <azonenberg@drawersteak.com>2016-12-12 17:05:06 +0800
commit01d8278e539933124de1336aa8ab70f49c6ac216 (patch)
tree835ec76259d82c74e975f52749e6360889e042af /backends/aiger/aiger.cc
parentc3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40 (diff)
parenta61c88f12215eb8bfa1db62aec7c2c95bb3cc702 (diff)
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Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'backends/aiger/aiger.cc')
-rw-r--r--backends/aiger/aiger.cc7
1 files changed, 7 insertions, 0 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index aefe5cf43..ab1fba6f1 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -163,6 +163,13 @@ struct AigerWriter
continue;
}
+ if (cell->type == "$anyconst")
+ {
+ for (auto bit : sigmap(cell->getPort("\\Y")))
+ ff_map[bit] = bit;
+ continue;
+ }
+
log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
}