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author | Clifford Wolf <clifford@clifford.at> | 2014-10-26 20:33:10 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-26 20:33:10 +0100 |
commit | 70b2efdb05f24eb7a9f3e2f456e5452fff94a15e (patch) | |
tree | faf75a016ba15af55c022e056d346a5a98193831 /README | |
parent | 26cbe4a4e56c0b95483b7568914d0402ef955b72 (diff) | |
download | yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.tar.gz yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.tar.bz2 yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.zip |
Added support for $readmemh/$readmemb
Diffstat (limited to 'README')
-rw-r--r-- | README | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -384,7 +384,6 @@ Other Unsorted TODOs - Implement missing Verilog 2005 features: - Support for real (float) const. expressions and parameters - - ROM modeling using $readmemh/$readmemb in "initial" blocks - Ignore what needs to be ignored (e.g. drive and charge strengths) - Check standard vs. implementation to identify missing features |