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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-16 17:32:11 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-16 17:32:11 +0100 |
| commit | 6d1502b9484a445e5184bdf622f87fcd14d0a0f9 (patch) | |
| tree | 76180477f9ab2c690c9138b028dd75a12639ddb8 /README | |
| parent | e8231ee46b79a0d24e3b8c5b75f75fc71efcd0d3 (diff) | |
| download | yosys-6d1502b9484a445e5184bdf622f87fcd14d0a0f9.tar.gz yosys-6d1502b9484a445e5184bdf622f87fcd14d0a0f9.tar.bz2 yosys-6d1502b9484a445e5184bdf622f87fcd14d0a0f9.zip | |
Added support for "always @(*)"
Diffstat (limited to 'README')
| -rw-r--r-- | README | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -74,7 +74,7 @@ or using a simple synthesis script: proc; opt; techmap; opt write_verilog synth.v - $ ././yosys synth.ys + $ ./yosys synth.ys It is also possible to only have the synthesis commands but not the read/write commands in the synthesis script: |